Hi Geert,
Thank you for the review.
On Mon, Aug 11, 2025 at 2:34 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Fri, 8 Aug 2025 at 23:52, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Document the USB2 PHY controller for the Renesas RZ/T2H (r9a09g077) and
> > RZ/N2H (r9a09g087) SoCs. These SoCs share the same PHY block, which is
> > similar to the one on RZ/G2L but differs in clocks, resets, and register
> > bits. To account for these differences, a new compatible string
> > `renesas,usb2-phy-r9a09g077` is introduced.
> >
> > The RZ/N2H SoC uses the same PHY as RZ/T2H, so it reuses the RZ/T2H
> > compatible string as a fallback.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
>
> > @@ -120,6 +126,17 @@ allOf:
> > required:
> > - resets
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,usb2-phy-r9a09g077
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 2
> > + resets: false
>
> By the time this hits upstream, you will probably have reset support
> for RZ/T2H and RZ/N2H, so you just add renesas,usb2-phy-r9a09g077
> to the conditional section above?
>
But the above will still be true as MRCTLA/E/I/M register doesn't have
any bits to reset USB{PHY} or am I missing something?
Cheers,
Prabhakar
