Hi Prabhakar,
On Fri, 8 Aug 2025 at 23:13, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> On Fri, Aug 8, 2025 at 8:51 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > On Fri, 1 Aug 2025 at 17:46, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Document the pin and GPIO controller IP for the Renesas RZ/T2H
> > > (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI
> > > header file used by both the bindings and the driver.
> > >
> > > The RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins.
> > > Both share the same controller architecture; separate compatible
> > > strings are added for each SoC to distinguish them.
> > >
> > > Co-developed-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > > v3->v4:
> > > - Used patternProperties for pin configuration nodes
> > > - Expanded example nodes
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> > > + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> > > + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> > > + };
> > > +
> > > + sd0-sd-tmp-pins {
> > > + pins = "RIIC0_SDA", "RIIC0_SCL";
> > > + input-enable;
> > > + };
> >
> > Please drop this subnode? It totally confuses me ;-)
> >
> I did drop this in the v5 series [0].
>
> https://lore.kernel.org/all/20250808133017.2053637-2-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
My bad; I had reviewed v4, but forgot to send them.
When I discovered my old draft, I just sent it out...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
