On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add support for configuring the PFC_OEN register on the RZ/G3E SoC to
> enable output-enable control for specific pins. On this SoC, certain
> pins such as TXC_TXCLK need to support switching between input and
> output modes depending on the PHY interface mode (e.g., MII vs RGMII).
> This functionality maps to the 'output-enable' property in the device
> tree and requires explicit control via the PFC_OEN register.
>
> This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1,
> PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable
> support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these
> pin names to their respective OEN bit positions, and the corresponding
> callbacks are wired into the RZ/G3E SoC configuration using the generic
> rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO
> configuration for the PB, PE, and PL ports is updated to use the variable
> port pack macro, enabling per-pin configuration necessary for OEN handling.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
