Hi Prabhakar,
On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Prepare for supporting SoCs with varying OEN register locations by
> parameterizing the OEN offset in the rzg2l driver. Introduce an `oen`
> field in the rzg2l_register_offsets structure and update rzg2l_read_oen(),
> rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use
> this offset instead of the hard-coded ETH_MODE value.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -3164,7 +3167,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
> }
>
> cache->qspi = readb(pctrl->base + QSPI);
> - cache->eth_mode = readb(pctrl->base + ETH_MODE);
> + cache->eth_mode = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
You still have the eth_mode name in the rzg2l_pinctrl_reg_cache
structure; probably you want to rename that as well.
In addition, it is saved/restored unconditionally, even if regs.oen
is zero, which is the case for RZ/V2H, RZ/V2N, and RZ/G3E until
[PATCH v2 5/7].
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
