On Fri, 01 Aug 2025 16:45:48 +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Document the pin and GPIO controller IP for the Renesas RZ/T2H > (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI > header file used by both the bindings and the driver. > > The RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins. > Both share the same controller architecture; separate compatible > strings are added for each SoC to distinguish them. > > Co-developed-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > v3->v4: > - Used patternProperties for pin configuration nodes > - Expanded example nodes > > v2->v3: > - Dropped refference to gpio.txt instead pointed to > in include/dt-bindings/gpio/gpio.h. > > v1->v2: > - Added a new DT binding file > --- > .../pinctrl/renesas,rzt2h-pinctrl.yaml | 177 ++++++++++++++++++ > .../pinctrl/renesas,r9a09g077-pinctrl.h | 22 +++ > 2 files changed, 199 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml > create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
