Re: [PATCH v4 1/3] dt-bindings: media: Add bindings for the RZ/V2H IVC block

["Lad, Prabhakar" <prabhakar.csengg@xxxxxxxxx>]

Hi Daniel,

Thank you for the patch.

On Mon, Jul 14, 2025 at 4:28 PM Daniel Scally
<dan.scally@xxxxxxxxxxxxxxxx> wrote:
>
> The RZ/V2H SoC has a block called the Input Video Control block which
> feeds image data into the Image Signal Processor. Add dt bindings to
> describe the IVC.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Signed-off-by: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
> ---
> Changes in v3:
>
>         - Rename from rzv2h-ivc.yaml to r9a09g057-ivc.yaml
>         - Update clock and reset names
>
> Changes in v2:
>
>         - compatible matches filename
>         - Added power-domains
>         - Aligned clock and reset entries on opening "<"
>         - Removed status = "okay"; from example
> ---
>  .../bindings/media/renesas,r9a09g057-ivc.yaml      | 103 +++++++++++++++++++++
>  1 file changed, 103 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..3ecccf0a4b05ffcf90c130924bfe50065b06f87e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/renesas,r9a09g057-ivc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H Input Video Control Block
> +
s/ RZ/V2H/RZ/V2HP
The 'P' variant is the one which has the Mali-C55 (also in the commit message).

Rest LGTM.

Cheers,
Prabhakar

> +maintainers:
> +  - Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
> +
> +description:
> +  The IVC block is a module that takes video frames from memory and feeds them
> +  to the Image Signal Processor for processing.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g057-ivc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Input Video Control block register access clock
> +      - description: Video input data AXI bus clock
> +      - description: ISP system clock
> +
> +  clock-names:
> +    items:
> +      - const: reg
> +      - const: axi
> +      - const: isp
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: Input Video Control block register access reset
> +      - description: Video input data AXI bus reset
> +      - description: ISP core reset
> +
> +  reset-names:
> +    items:
> +      - const: reg
> +      - const: axi
> +      - const: isp
> +
> +  port:
> +    $ref: /schemas/graph.yaml#/properties/port
> +    description: Output parallel video bus
> +
> +    properties:
> +      endpoint:
> +        $ref: /schemas/graph.yaml#/properties/endpoint
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - resets
> +  - reset-names
> +  - port
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    isp-input@16040000 {
> +      compatible = "renesas,r9a09g057-ivc";
> +      reg = <0x16040000 0x230>;
> +
> +      clocks = <&cpg CPG_MOD 0xe3>,
> +               <&cpg CPG_MOD 0xe4>,
> +               <&cpg CPG_MOD 0xe5>;
> +      clock-names = "reg", "axi", "isp";
> +
> +      power-domains = <&cpg>;
> +
> +      resets = <&cpg 0xd4>,
> +               <&cpg 0xd1>,
> +               <&cpg 0xd3>;
> +      reset-names = "reg", "axi", "isp";
> +
> +      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
> +
> +      port {
> +        ivc_out: endpoint {
> +          remote-endpoint = <&isp_in>;
> +        };
> +      };
> +    };
> +...
>
> --
> 2.34.1
>
>