Before the MIPI DSI clock source can be configured, the target divide ratio needs to be known. Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx> --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 4ad0be03a5b4..a8796df43f75 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -7,6 +7,7 @@ #include <linux/bitfield.h> #include <linux/clk.h> +#include <linux/clk/renesas.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/io.h> @@ -666,6 +667,22 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, drm_bridge_add(&dsi->bridge); + /* Report required division ratio setting for the MIPI clock dividers + * Assume the default clock source is FOUTPOSTDIV (PLL/2) being fed to the DSI-PHY, but also + * the DSI-PHY must be 16x the MIPI-DSI HS clock. + * + * pllclk/2 = vclk * DSI divider + * pllclk = vclk * DSI divider * 2 + * + * hsclk = (vclk * DSI divider * 2) / 16 + * + * vclk * bpp = hsclk * 8 * num_lanes + * vclk * bpp = ((vclk * DSI divider * 2) / 16) * 8 * num_lanes + * which simplifies to... + * DSI divider = bpp / num_lanes + */ + rzg2l_cpg_dsi_div_set_divider(mipi_dsi_pixel_format_to_bpp(dsi->format) / dsi->lanes); + return 0; } -- 2.49.0
