On 08/07/2025 18:34, Bjorn Helgaas wrote: > On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> >> >> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express >> Base Specification 4.0. It is designed for root complex applications and >> features a single-lane (x1) implementation. Add documentation for it. > >> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml > > The "r9a08g045s33" in the filename seems oddly specific. Does it > leave room for descendants of the current chip that will inevitably be > added in the future? Most bindings are named with a fairly generic > family name, e.g., "fsl,layerscape", "hisilicon,kirin", "intel, > keembay", "samsung,exynos", etc. > Bindings should be named by compatible, not in a generic way, so name is correct. It can always grow with new compatibles even if name matches old one, it's not a problem. Best regards, Krzysztof
