From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Update the rzv2h_wdt driver to obtain the clock division ratio (`cks_div`)
from OF match data instead of using a hardcoded value. This allows the
driver to support SoCs where the clock divider differs from the default
value of 256.
This change is a preparatory step for supporting the RZ/T2H SoC, which
requires a divider value of 8192.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
drivers/watchdog/rzv2h_wdt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index d64d29709160..c2f39dd56687 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -36,7 +36,6 @@
#define WDTRCR_RSTIRQS BIT(7)
#define MAX_TIMEOUT_CYCLES 16384
-#define CLOCK_DIV_BY_256 256
#define WDT_DEFAULT_TIMEOUT 60U
@@ -48,6 +47,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
struct rzv2h_of_data {
u8 cks_min;
u8 cks_max;
+ u16 cks_div;
};
struct rzv2h_wdt_priv {
@@ -238,7 +238,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(priv->rstc),
"failed to get cpg reset");
- priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DIV_BY_256) /
+ priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * priv->of_data->cks_div) /
clk_get_rate(priv->oscclk);
dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);
@@ -265,6 +265,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
static const struct rzv2h_of_data rzv2h_wdt_of_data = {
.cks_min = WDTCR_CKS_CLK_1,
.cks_max = WDTCR_CKS_CLK_256,
+ .cks_div = 256,
};
static const struct of_device_id rzv2h_wdt_ids[] = {
--
2.49.0
