[PATCH 6/6] ARM: dts: renesas: rza2mbtc: initial board support

[Magnus Damm <damm@xxxxxxxxxxxxx>]

From: Magnus Damm <damm@xxxxxxxxxxxxx>

Add initial support for the RZA2MBTC board which is based on the RZ/A2M by
Renesas Electronics. Included in this patch are DTS nodes for serial console,
on-board SPI flash as well as RMII Ethernet.

Signed-off-by: Magnus Damm <damm@xxxxxxxxxxxxx>
---

 Applies to next-20250704

 arch/arm/boot/dts/renesas/Makefile                  |    1 
 work/arch/arm/boot/dts/renesas/r7s9210-rza2mbtc.dts |  133 +++++++++++++++++++
 2 files changed, 134 insertions(+)
 
--- 0006/arch/arm/boot/dts/renesas/Makefile
+++ work/arch/arm/boot/dts/renesas/Makefile	2025-07-05 22:03:46.456578459 +0900
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 	r7s72100-gr-peach.dtb \
 	r7s72100-rskrza1.dtb \
 	r7s9210-gr-mango.dtb \
+	r7s9210-rza2mbtc.dtb \
 	r7s9210-rza2mevb.dtb \
 	r8a73a4-ape6evm.dtb \
 	r8a7740-armadillo800eva.dtb \
--- /dev/null
+++ work/arch/arm/boot/dts/renesas/r7s9210-rza2mbtc.dts	2025-07-05 22:03:21.996442287 +0900
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZ/A2M BTC board
+ *
+ * Based on RZA2MEVB, Copyright (C) 2018 Renesas Electronics
+ */
+
+/dts-v1/;
+#include "r7s9210.dtsi"
+#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
+
+/ {
+	model = "RZA2MBTC";
+	compatible = "aprg,rza2mbtc", "renesas,r7s9210";
+
+	aliases {
+		serial0 = &scif1;
+		spi0 = &rpc0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>; /* EXTAL: Y2: ECS-240-8-47B-7KM-TR (24MHz) */
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+&ostm1 {
+	status = "okay";
+};
+
+&rpc0 {
+	status = "okay";
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "mcuboot";
+				reg = <0x00000000 0x00018000>;
+				read-only;
+			};
+			partition@18000 {
+				label = "mcuboot-scratch";
+				reg = <0x00018000 0x00008000>;
+				read-only;
+			};
+			partition@20000 {
+				label = "mcuboot-primary";
+				reg = <0x00020000 0x00060000>;
+				read-only;
+			};
+			partition@80000 {
+				label = "mcuboot-secondary";
+				reg = <0x00080000 0x00060000>;
+			};
+			partition@e0000 {
+				label = "u-boot-env";
+				reg = <0x000e0000 0x00010000>;
+			};
+			partition@f0000 {
+				label = "factory-data";
+				reg = <0x000f0000 0x00010000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ether1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth1_pins>;
+	status = "okay";
+	phy-mode = "rmii";
+
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0007.c0f0",
+			   "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&pinctrl {
+	scif1_pins: serial0 {
+		pinmux = <RZA2_PINMUX(PORTJ, 2, 4)>, /* H1:1 PJ_2 (TxD1) */
+			 <RZA2_PINMUX(PORTJ, 1, 4)>; /* H1:2 PJ_1 (RxD1) */
+	};
+
+	eth1_pins: eth1 {
+		pinmux = <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
+			 <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
+			 <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
+			 <RZA2_PINMUX(PORTK, 0, 7)>, /* RMII1_TXDEN */
+			 <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
+			 <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
+			 <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
+			 <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
+			 <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
+			 <RZA2_PINMUX(PORT3, 1, 7)>; /* RMII1_RXER */
+	};
+};
+
+&rtc_x1_clk {
+	clock-frequency = <32768>; /* RTC_X1: Y1: ECS-.327-12.5-1210-TR (32kHz) */
+};
+
+&scif1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&scif1_pins>;
+
+	status = "okay";
+};