[PATCH 5/6] ARM: dts: renesas: gr-mango: initial board support

[Magnus Damm <damm@xxxxxxxxxxxxx>]

From: Magnus Damm <damm@xxxxxxxxxxxxx>

Add initial support for the GR-Mango board which is based on RZ/A2M by Renesas
Electronics. Included in this patch are DTS nodes for serial console as well
as MII Ethernet.

Signed-off-by: Magnus Damm <damm@xxxxxxxxxxxxx>
---

 Applies to next-20250704

 arch/arm/boot/dts/renesas/Makefile                  |    1 
 work/arch/arm/boot/dts/renesas/r7s9210-gr-mango.dts |   87 +++++++++++++++++++
 2 files changed, 88 insertions(+)
 
--- 0001/arch/arm/boot/dts/renesas/Makefile
+++ work/arch/arm/boot/dts/renesas/Makefile	2025-07-05 21:57:56.886566015 +0900
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 	r7s72100-genmai.dtb \
 	r7s72100-gr-peach.dtb \
 	r7s72100-rskrza1.dtb \
+	r7s9210-gr-mango.dtb \
 	r7s9210-rza2mevb.dtb \
 	r8a73a4-ape6evm.dtb \
 	r8a7740-armadillo800eva.dtb \
--- /dev/null
+++ work/arch/arm/boot/dts/renesas/r7s9210-gr-mango.dts	2025-07-05 21:56:25.214033636 +0900
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the GRMANGO board
+ *
+ * Based on RZA2MEVB, Copyright (C) 2018 Renesas Electronics
+ */
+
+/dts-v1/;
+#include "r7s9210.dtsi"
+#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
+
+/ {
+	model = "GRMANGO";
+	compatible = "renesas,grmango", "renesas,r7s9210";
+
+	aliases {
+		serial0 = &scif0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>;	/* EXTAL: X2: FCXO-07(24MHz) */
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+&ostm1 {
+	status = "okay";
+};
+
+&ether1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth1_pins>;
+	status = "okay";
+	phy-mode = "mii";
+
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0007.c0f0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&pinctrl {
+	scif0_pins: serial0 {
+		pinmux = <RZA2_PINMUX(PORT4, 2, 1)>,	/* TxD0 */
+			 <RZA2_PINMUX(PORT4, 1, 1)>;	/* RxD0 */
+	};
+
+	eth1_pins: eth1 {
+		pinmux = <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
+			 <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
+			 <RZA2_PINMUX(PORTC, 0, 3)>, /* ET1_TXCLK */
+			 <RZA2_PINMUX(PORTC, 4, 3)>, /* ET1_TXER */
+			 <RZA2_PINMUX(PORTK, 0, 1)>, /* ET1_TXEN */
+			 <RZA2_PINMUX(PORTK, 1, 1)>, /* ET1_TXD0 */
+			 <RZA2_PINMUX(PORTK, 2, 1)>, /* ET1_TXD1 */
+			 <RZA2_PINMUX(PORTC, 1, 3)>, /* ET1_TXD2 */
+			 <RZA2_PINMUX(PORTC, 2, 3)>, /* ET1_TXD3 */
+			 <RZA2_PINMUX(PORTK, 3, 1)>, /* ET1_RXCLK */
+			 <RZA2_PINMUX(PORT3, 1, 1)>, /* ET1_RXER */
+			 <RZA2_PINMUX(PORTC, 5, 3)>, /* ET1_RXDV */
+			 <RZA2_PINMUX(PORTK, 4, 1)>, /* ET1_RXD0 */
+			 <RZA2_PINMUX(PORT3, 5, 1)>, /* ET1_RXD1 */
+			 <RZA2_PINMUX(PORTC, 6, 3)>, /* ET1_RXD2 */
+			 <RZA2_PINMUX(PORTC, 7, 3)>, /* ET1_RXD3 */
+			 <RZA2_PINMUX(PORT3, 2, 1)>, /* ET1_CRS */
+			 <RZA2_PINMUX(PORTC, 3, 3)>; /* ET1_COL */
+	};
+};
+
+&scif0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&scif0_pins>;
+
+	status = "okay";
+};