Hi Geert,
On Fri, Jul 4, 2025 at 12:52 AM Lad, Prabhakar
<prabhakar.csengg@xxxxxxxxx> wrote:
>
> Hi Geert,
>
> Thank you for the review.
>
> On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> >
> > Hi Prabhakar,
> >
> > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> > > interrupt-controller;
> > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > > };
> > > +
> > > + sdhi0: mmc@92080000 {
> > > + compatible = "renesas,sdhi-r9a09g077",
> > > + "renesas,sdhi-r9a09g057";
> > > + reg = <0x0 0x92080000 0 0x10000>;
> > > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 1212>,
> >
> > 1112?
> >
> Agreed (and below).
>
Sorry, it is indeed 1212/1213 as the bits belong to MSTPCRM register.
Cheers,
Prabhakar
