Hi Geert,
Thank you for the review.
On Tue, Jul 1, 2025 at 1:08 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Add XSPI node to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -280,6 +280,29 @@ sys: system-controller@10430000 {
> > resets = <&cpg 0x30>;
> > };
> >
> > + xspi: spi@11030000 {
> > + compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
> > + reg = <0 0x11030000 0 0x10000>,
> > + <0 0x20000000 0 0x10000000>;
> > + reg-names = "regs", "dirmap";
> > + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "pulse", "err_pulse";
> > + clocks = <&cpg CPG_MOD 0x9f>,
> > + <&cpg CPG_MOD 0xa0>,
> > + <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>,
> > + <&cpg CPG_MOD 0xa1>;
> > + clock-names = "ahb", "axi", "spi", "spix2";
> > + assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
> > + assigned-clock-rates = <133333334>;
>
> Same question as [PATCH 1/4].
>
Sure, I'll move this to the board DTS, and also add the comment below
for clarity.
/*
* MT25QU512ABB8E12 flash chip is capable of running at 166MHz
* clock frequency. Set the maximum clock frequency to 133MHz
* supported by the RZ/V2H SoC.
*/
Cheers,
Prabhakar
