Hi Geert, Thank you for the review. On Wed, Jul 2, 2025 at 7:23 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > On Wed, 2 Jul 2025 at 15:37, Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > > > Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas > > > RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as > > > a core clock for the SDHI IP and operates at 800MHz. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Thanks for your patch! > > > > > include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + > > > include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > > i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp. > > renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and > > renesas-devel. > > Looks like I can do without the split, as renesas-r9a09g087-dt-binding-defs > is based on renesas-r9a09g077-dt-binding-defs. > Great! I mainly did this to reduce the load on DT maintainers. Cheers, Prabhakar
