On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
> register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
> operating at 800MHz.
>
> Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
> module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
> clock source.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
