Hi Geert,
On Mon, Jun 30, 2025 at 9:10 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Sat, 28 Jun 2025 at 13:57, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> >
> > Update the RSCI binding to support an optional secondary clock input on
> > the RZ/T2H SoC. At boot, the RSCI operates using the default synchronous
> > clock (PCLKM core clock), which is enabled by the bootloader. However, to
> > support a wider range of baud rates, the hardware also requires an
> > asynchronous external clock input. Clock selection is controlled
> > internally by the CCR3 register in the RSCI block.
> >
> > Due to an incomplete understanding of the hardware, the original binding
> > defined only a single clock ("fck"), which is insufficient to describe the
> > full capabilities of the RSCI on RZ/T2H. This update corrects the binding
> > by allowing up to three clocks and defining the `clock-names` as
> > "operation", "bus", and optionally "sck" for the asynchronous clock input.
> >
> > This is an ABI change, as it modifies the expected number and names of
> > clocks. However, since there are no in-kernel consumers of this binding
> > yet, the change is considered safe and non-disruptive.
> >
> > Also remove the unneeded `serial0` alias from the DTS example and use
> > the R9A09G077_CLK_PCLKM macro for core clock.
> >
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> > ---
> > v12->v13:
> > - Rebased on latest linux-next.
> > - Updated commit message to clarify the ABI change.
>
> Thanks for the update!
>
> > - Used `R9A09G077_CLK_PCLKM` macro for core clock
>
> Unfortunately include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> is not yet upstream, so you cannot use its definitions yet outside
> renesas-clk.
>
Thanks for pointing that out.
Cheers,
Prabhakar
