As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64 bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes. During testing it is found that, if the DMA buffer is not aligned to 128 bit it fallback to PIO mode. In such cases, 64-bit access is much more efficient than the current 16-bit. Biju Das (2): mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode mmc: renesas_sdhi: Enable 64-bit polling mode drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +- drivers/mmc/host/tmio_mmc.h | 12 +++++++ drivers/mmc/host/tmio_mmc_core.c | 32 +++++++++++++++++++ include/linux/platform_data/tmio.h | 3 ++ 4 files changed, 49 insertions(+), 1 deletion(-) -- 2.43.0