As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
drivers/mmc/host/tmio_mmc.h | 12 +++++++++++
drivers/mmc/host/tmio_mmc_core.c | 32 ++++++++++++++++++++++++++++++
include/linux/platform_data/tmio.h | 3 +++
3 files changed, 47 insertions(+)
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index d730b7633ae1..823143a98941 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -242,6 +242,18 @@ static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
}
+static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
+ u64 *buf, int count)
+{
+ ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
+static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
+ const u64 *buf, int count)
+{
+ iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
u16 val)
{
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 2cec463b5e00..c4eacf9545ba 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -350,6 +350,38 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
/*
* Transfer the data
*/
+
+ if (host->pdata->flags & TMIO_MMC_64BIT_DATA_PORT) {
+ u64 *buf64 = (u64 *)buf;
+ u64 data = 0;
+
+ if (count >= 8) {
+ if (is_read)
+ sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT,
+ buf64, count >> 3);
+ else
+ sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT,
+ buf64, count >> 3);
+ }
+
+ /* if count was multiple of 8 */
+ if (!(count & 0x7))
+ return;
+
+ buf64 += count >> 3;
+ count %= 8;
+
+ if (is_read) {
+ sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT, &data, 1);
+ memcpy(buf64, &data, count);
+ } else {
+ memcpy(&data, buf64, count);
+ sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT, &data, 1);
+ }
+
+ return;
+ }
+
if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
u32 data = 0;
u32 *buf32 = (u32 *)buf;
diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_data/tmio.h
index b060124ba1ae..426291713b83 100644
--- a/include/linux/platform_data/tmio.h
+++ b/include/linux/platform_data/tmio.h
@@ -47,6 +47,9 @@
/* Some controllers have a CBSY bit */
#define TMIO_MMC_HAVE_CBSY BIT(11)
+/* Some controllers have a 64-bit wide data port register */
+#define TMIO_MMC_64BIT_DATA_PORT BIT(12)
+
struct tmio_mmc_data {
void *chan_priv_tx;
void *chan_priv_rx;
--
2.43.0
