On Wed, Jun 25, 2025 at 04:07:58PM +0300, Claudiu Beznea wrote: > On 18.06.2025 20:42, Manivannan Sadhasivam wrote: > > On Fri, May 30, 2025 at 02:19:13PM +0300, Claudiu wrote: > >> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > >> > >> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express > >> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions > >> only as a root complex, with a single-lane (x1) configuration. The > >> controller includes Type 1 configuration registers, as well as IP > >> specific registers (called AXI registers) required for various adjustments. > This is how HW manual suggest to do it. The manual is open, it can be > downloaded from [1]. Chapter that describes the steps implemented here is > 34.4.2.4 Issuing Special Requests. > > Steps to reach the HW manual: > 1/ click "RZ/G3S Group User's Manual: Hardware" button > 2/ click confirm > 3/ open the archive > 4/ go to r01uh1014ej0110-rzg3s-users-manual-hardware -> Deliverables > 5/ open r01uh1014ej0110-rzg3s.pdf Nice that the manual is public! URLs are a great invention; it's too bad when we need directions for where to click, etc, in addition to the URL. Maybe one or both of these URLs could be included in the commit log. > [1] > https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11ghz-cpu-and-dual-core-cortex-m33-250mhz?queryID=695cc067c2d89e3f271d43656ede4d12 https://www.renesas.com/en/document/mah/rzg3s-group-users-manual-hardware?r=25458591
