Hi John,
On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@xxxxxxxxxxxxxx> wrote:
> Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
> IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
> clocks needed by these two GBETH IPs.
>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Tested-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> ---
>
> v2:
> No changes but resending without dt-bindings patch
>
> v3:
> Uses underscores instead of dashes in clock names
Thanks for the update!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> +
> /* Mux clock tables */
> +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxc_rx_clk" };
> +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txc_tx_clk" };
> +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxc_rx_clk" };
> +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txc_tx_clk" };
I have to ask you again: these still differ from the similar names used
on RZ/V2H. Is there a reason for that? Will that cause issues later?
Or is this to be sorted out only when the PHY driver will start
supporting these clocks?
> static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
> static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
