From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
The RZ/N2H (R9A09G087) SoC from Renesas shares a similar pin controller
architecture with the RZ/T2H (R9A09G077) SoC, differing primarily in the
number of supported pins-576 on RZ/N2H versus 729 on RZ/T2H.
Add the necessary pin configuration data and compatible string to enable
support for the RZ/N2H SoC in the RZ/T2H pinctrl driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v1->v2:
- New patch
---
drivers/pinctrl/renesas/Kconfig | 5 +++--
drivers/pinctrl/renesas/pinctrl-rzt2h.c | 17 +++++++++++++++++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index eab8e00a2b24..ec94e6d6acd5 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -45,6 +45,7 @@ config PINCTRL_RENESAS
select PINCTRL_RZG2L if ARCH_R9A09G056
select PINCTRL_RZG2L if ARCH_R9A09G057
select PINCTRL_RZT2H if ARCH_R9A09G077
+ select PINCTRL_RZT2H if ARCH_R9A09G087
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -251,9 +252,9 @@ config PINCTRL_RZN1
This selects pinctrl driver for Renesas RZ/N1 devices.
config PINCTRL_RZT2H
- bool "pin control support for RZ/T2H"
+ bool "pin control support for RZ/N2H and RZ/T2H"
depends on OF
- depends on ARCH_R9A09G077 || COMPILE_TEST
+ depends on (ARCH_R9A09G087 || ARCH_R9A09G077) || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
index d1dfe4b9a085..613f75337ee6 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
@@ -763,6 +763,12 @@ static const u8 r9a09g077_gpio_configs[] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
};
+static const u8 r9a09g087_gpio_configs[] = {
+ 0x1f, 0xff, 0xff, 0x1f, 0, 0xfe, 0xff, 0, 0x7e, 0xf0, 0xff, 0x1,
+ 0xff, 0xff, 0xff, 0, 0xe0, 0xff, 0xff, 0, 0xff, 0xff, 0xff, 0x1,
+ 0xe0, 0xff, 0xff, 0x7f, 0, 0xfe, 0xff, 0x7f, 0, 0xfc, 0x7f,
+};
+
static struct rzt2h_pinctrl_data r9a09g077_data = {
.port_pins = rzt2h_gpio_names,
.n_port_pins = ARRAY_SIZE(r9a09g077_gpio_configs) * RZT2H_PINS_PER_PORT,
@@ -770,11 +776,22 @@ static struct rzt2h_pinctrl_data r9a09g077_data = {
.n_ports = ARRAY_SIZE(r9a09g077_gpio_configs),
};
+static struct rzt2h_pinctrl_data r9a09g087_data = {
+ .port_pins = rzt2h_gpio_names,
+ .n_port_pins = ARRAY_SIZE(r9a09g087_gpio_configs) * RZT2H_PINS_PER_PORT,
+ .port_pin_configs = r9a09g087_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a09g087_gpio_configs),
+};
+
static const struct of_device_id rzt2h_pinctrl_of_table[] = {
{
.compatible = "renesas,r9a09g077-pinctrl",
.data = &r9a09g077_data,
},
+ {
+ .compatible = "renesas,r9a09g087-pinctrl",
+ .data = &r9a09g087_data,
+ },
{ /* sentinel */ }
};
--
2.49.0
