Hi Fabrizio,
Thanks for the patch.
> -----Original Message-----
> From: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Sent: 24 June 2025 20:23
> Subject: [PATCH 1/6] clk: renesas: r9a09g057: Add entries for the RSPIs
>
> Add clock and reset entries for the Renesas RZ/V2H(P) RSPI IPs.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Cheers,
Biju
> ---
> drivers/clk/renesas/r9a09g057-cpg.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> index da908e820950..f39bd2e78312 100644
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -217,6 +217,24 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> BUS_MSTOP(5, BIT(13))),
> DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
> BUS_MSTOP(5, BIT(13))),
> + DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
> + BUS_MSTOP(11, BIT(0))),
> + DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
> + BUS_MSTOP(11, BIT(0))),
> + DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
> + BUS_MSTOP(11, BIT(0))),
> + DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
> + BUS_MSTOP(11, BIT(1))),
> + DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
> + BUS_MSTOP(11, BIT(1))),
> + DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
> + BUS_MSTOP(11, BIT(1))),
> + DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
> + BUS_MSTOP(11, BIT(2))),
> + DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
> + BUS_MSTOP(11, BIT(2))),
> + DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
> + BUS_MSTOP(11, BIT(2))),
> DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
> BUS_MSTOP(3, BIT(14))),
> DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
> @@ -349,6 +367,12 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
> DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
> DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
> DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
> + DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
> + DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
> + DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
> + DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
> + DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
> + DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
> DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
> DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
> DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
> --
> 2.34.1
