Hi Prabhakar,
On Fri, 13 Jun 2025 at 20:59, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> On Fri, Jun 13, 2025 at 4:37 PM Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > On Thu, Jun 12, 2025 at 4:47 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > On Tue, 10 Jun 2025 at 01:23, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > >
> > > > Add SDHI bindings for the Renesas RZ/T2H (a.k.a R9A09G077) and RZ/N2H
> > > > (a.k.a R9A09G087) SoCs. Use `renesas,sdhi-r9a09g057` as a fallback since
> > > > the SD/MMC block on these SoCs is identical to the one on RZ/V2H(P),
> > > > allowing reuse of the existing driver without modifications.
> > > >
> > > > Update the binding schema to reflect differences: unlike RZ/V2H(P),
> > > > RZ/T2H and RZ/N2H do not require the `resets` property and use only a
> > > > single clock instead of four.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> > > > +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> > > > @@ -129,59 +131,75 @@ allOf:
> > > > compatible:
> > > > contains:
> > > > enum:
> > > > - - renesas,sdhi-r9a09g057
> > > > - - renesas,rzg2l-sdhi
> > > > + - renesas,sdhi-r9a09g077
> > > > + - renesas,sdhi-r9a09g087
> > > > then:
> > > > properties:
> > > > + resets: false
> > > > clocks:
> > > > - items:
> > > > - - description: IMCLK, SDHI channel main clock1.
> > > > - - description: CLK_HS, SDHI channel High speed clock which operates
> > > > - 4 times that of SDHI channel main clock1.
> > > > - - description: IMCLK2, SDHI channel main clock2. When this clock is
> > > > - turned off, external SD card detection cannot be
> > > > - detected.
> > > > - - description: ACLK, SDHI channel bus clock.
> > > > + description: ACLK, SDHI channel bus clock.
> > >
> > > According to the documentation, this is the SDHI high speed clock...
> > >
> Actually re-reading the doc there are two clocks (I had missed the
> second clock earlier),
And I had missed the first, as it is not shown in Figure 7.1
("Block diagram of clock generation circuit" ;-)
> 1] ACLK, IMCLK from the PCLKAM which is 200MHz
> 2] SDHI_clkhs from PLL2 which is 800MHz
> Note, on RZ/V2H too the ACLK/IMCLK is 200MHz and clk_hs is 800MHz
>
> So, I'll represent them as below:
> clocks:
> items:
> - description: ACLK, IMCLK, SDHI channel bus and main clocks.
> - description: CLK_HS, SDHI channel High speed clock.
> clock-names:
> items:
> - const: aclk
> - const: clkh
>
> And for the ACLK, IMCLK which comes from peripheral module clock
> (PCLKAM) this will be a module clock and CLK_HS will have to be
> modelled as a CORE clock.
OK.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
