This is really only for testing. Not for upstream!
Not-signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
---
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 39845faec894..f3f391c609d3 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i3c/i3c.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include "rzg3s-smarc-switches.h"
@@ -172,6 +173,38 @@ a0 80 30 30 9c
};
};
+#undef I3C_BUS_PURE
+#ifdef I3C_BUS_PURE
+&i3c {
+ i2c-scl-hz = <1000000>;
+ i3c-scl-hz = <2000000>; /* slow Logic Analyzer here */
+ //i3c-scl-hz = <12500000>;
+ status = "okay";
+};
+#else
+&i3c {
+ i2c-scl-hz = <400000>; /* Max speed of the ADT7411 below */
+ /*
+ * 10MHz works somewhat with my 24MHz logic analyzer as well as
+ * signal width < 50ns for the legacy I2C filters
+ */
+ i3c-scl-hz = <10000000>;
+ status = "okay";
+
+ /* I2C bus from SMARC via PMOD6A. EEPROM driver only used to verify register content */
+ eeprom@1a {
+ compatible = "atmel,24c02";
+ reg = <0x1a 0 (I2C_FM | I2C_FILTER)>;
+ };
+
+ /* externel development board */
+ temp@4a {
+ compatible = "adi,adt7411";
+ reg = <0x4a 0 (I2C_FM | I2C_FILTER)>;
+ };
+};
+#endif
+
#if SW_CONFIG2 == SW_ON
/* SD0 slot */
&sdhi0 {
--
2.47.2
