From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined,
ensuring SoC-specific initialization is performed only when necessary.
This change prepares for RZ/V2H(P) SoC support while maintaining
compatibility with existing platforms.
Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
---
v6->v7:
- No changes
v5->v6:
- Renamed dphy_late_init to dphy_startup_late_init
- Added Reviewed-by tag from Laurent
v4->v5:
- Added Reviewed tag from Biju
v3->v4:
- No changes
v2->v3:
- No changes
v1->v2:
- No changes
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index afb427e678bd..12cb9f0d32fa 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -40,6 +40,7 @@ struct rzg2l_mipi_dsi;
struct rzg2l_mipi_dsi_hw_info {
int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
+ void (*dphy_startup_late_init)(struct rzg2l_mipi_dsi *dsi);
void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
u32 phy_reg_offset;
u32 link_reg_offset;
@@ -331,6 +332,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
+ if (dsi->info->dphy_startup_late_init)
+ dsi->info->dphy_startup_late_init(dsi);
+
hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
/*
* Global timings characteristic depends on high speed Clock Frequency
--
2.49.0
