Hi Geert,
Thank you for the review.
On Fri, Jun 6, 2025 at 2:37 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
> > different interrupt layout for the RIIC controller. Unlike other SoCs
> > with individual error interrupts, RZ/T2H uses a combined error interrupt
> > (EEI).
> >
> > Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
> > ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
> > interrupt.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/drivers/i2c/busses/i2c-riic.c
> > +++ b/drivers/i2c/busses/i2c-riic.c
> > @@ -326,6 +327,19 @@ static irqreturn_t riic_stop_isr(int irq, void *data)
> > return IRQ_HANDLED;
> > }
> >
> > +static irqreturn_t riic_eei_isr(int irq, void *data)
> > +{
> > + u8 icsr2 = riic_readb(data, RIIC_ICSR2);
> > +
> > + if (icsr2 & ICSR2_NACKF)
> > + return riic_tend_isr(irq, data);
> > +
> > + if (icsr2 & ICSR2_STOP)
> > + return riic_stop_isr(irq, data);
>
> Just wondering: can both ICSR2_NACKF and ICSR2_STOP be set?
> As riic_tend_isr() clears only ICSR2_NACKF, while riic_stop_isr()
> clears all bits, the two calls could be chained, if needed.
>
In the normal working scenario when verified both these bits were
never set together, hence I took this path.
Cheers,
Prabhakar
