Hi Marek,
On Sat, 31 May 2025 at 00:55, Marek Vasut
<marek.vasut+renesas@xxxxxxxxxxx> wrote:
> The V4H Sparrow Hawk board supplies PCIe controller input clock and PCIe
> bus clock from separate outputs of Renesas 9FGV0441 clock generator chip.
> Describe this split bus configuration in the board DT. The topology looks
> as follows:
>
> ____________ _____________
> | R-Car PCIe | | PCIe device |
> | | | |
> | PCIe RX<|==================|>PCIe TX |
> | PCIe TX<|==================|>PCIe RX |
> | | | |
> | PCIe CLK<|======.. ..======|>PCIe CLK |
> '------------' || || '-------------'
> || ||
> ____________ || ||
> | 9FGV0441 | || ||
> | | || ||
> | CLK DIF0<|======'' ||
> | CLK DIF1<|==========''
> | CLK DIF2<|
> | CLK DIF3<|
> '------------'
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
Thanks for your patch!
> V2: Use pciec0_rp/pciec1_rp phandles to refer to root port moved to core r8a779g0.dtsi
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
I understand this has a hard dependency on [PATCH v2 1/3] (and on
enabling CONFIG_PCI_PWRCTRL_SLOT), so I cannot apply this before that
patch is upstream?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
