On Fri, May 30, 2025 at 03:31:35PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a > different interrupt layout for the RIIC controller. Unlike other SoCs > with individual error interrupts, RZ/T2H uses a combined error interrupt > (EEI). > > Introduce a new IRQ descriptor table for RZ/T2H, along with a custom > ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared > interrupt. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Tested-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> # on RZ/A1
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