On Sun, May 25, 2025 at 06:04:04PM +0200, Marek Vasut wrote:
> The V4H Sparrow Hawk board supplies PCIe controller input clock and PCIe
> bus clock from separate outputs of Renesas 9FGV0441 clock generator chip.
> Describe this split bus configuration in the board DT. The topology looks
> as follows:
>
> ____________ _____________
> | R-Car PCIe | | PCIe device |
> | | | |
> | PCIe RX<|==================|>PCIe TX |
> | PCIe TX<|==================|>PCIe RX |
> | | | |
> | PCIe CLK<|======.. ..======|>PCIe CLK |
> '------------' || || '-------------'
> || ||
> ____________ || ||
> | 9FGV0441 | || ||
> | | || ||
> | CLK DIF0<|======'' ||
> | CLK DIF1<|==========''
> | CLK DIF2<|
> | CLK DIF3<|
> '------------'
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
> ---
> Cc: Bartosz Golaszewski <brgl@xxxxxxxx>
> Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
> Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
> Cc: Magnus Damm <magnus.damm@xxxxxxxxx>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Cc: Rob Herring <robh@xxxxxxxxxx>
> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> Cc: linux-pci@xxxxxxxxxxxxxxx
> Cc: linux-renesas-soc@xxxxxxxxxxxxxxx
> ---
> .../dts/renesas/r8a779g3-sparrow-hawk.dts | 45 ++++++++++++++++++-
> 1 file changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
> index b8698e07add56..7c050a56290fd 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
> @@ -130,6 +130,13 @@ mini_dp_con_in: endpoint {
> };
> };
>
> + /* Page 26 / PCIe.0/1 CLK */
> + pcie_refclk: clk-x8 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> reg_1p2v: regulator-1p2v {
> compatible = "regulator-fixed";
> regulator-name = "fixed-1.2V";
> @@ -404,6 +411,14 @@ i2c0_mux2: i2c@2 {
> reg = <2>;
> #address-cells = <1>;
> #size-cells = <0>;
> +
> + /* Page 26 / PCIe.0/1 CLK */
> + pcie_clk: clk@68 {
> + compatible = "renesas,9fgv0441";
> + reg = <0x68>;
> + clocks = <&pcie_refclk>;
> + #clock-cells = <1>;
> + };
> };
>
> i2c0_mux3: i2c@3 {
> @@ -487,24 +502,50 @@ msiof1_snd_endpoint: endpoint {
>
> /* Page 26 / 2230 Key M M.2 */
> &pcie0_clkref {
> - clock-frequency = <100000000>;
> + status = "disabled";
> };
>
> &pciec0 {
> + clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>;
> reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
> status = "okay";
> +
> + /* PCIe bridge, Root Port */
> + pci@0,0 {
PCIe bridge mostly is integrated into the SoC itself. So it should be defined
in the SoC dtsi. Only the vpcie3v3-supply is board specific, so it should live
in board dts.
- Mani
> + #address-cells = <3>;
> + #size-cells = <2>;
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + compatible = "pciclass,0604";
> + device_type = "pci";
> + clocks = <&pcie_clk 1>;
> + vpcie3v3-supply = <®_3p3v>;
> + ranges;
> + };
> };
>
> /* Page 25 / PCIe to USB */
> &pcie1_clkref {
> - clock-frequency = <100000000>;
> + status = "disabled";
> };
>
> &pciec1 {
> + clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>;
> /* uPD720201 is PCIe Gen2 x1 device */
> num-lanes = <1>;
> reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
> status = "okay";
> +
> + /* PCIe bridge, Root Port */
> + pci@0,0 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + compatible = "pciclass,0604";
> + device_type = "pci";
> + clocks = <&pcie_clk 3>;
> + vpcie3v3-supply = <®_3p3v>;
> + ranges;
> + };
> };
>
> &pfc {
> --
> 2.47.2
>
--
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