On Wed, Aug 13, 2025 at 01:46:55PM -0500, Alex Elder wrote: > Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in > the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual > in that only the combo PHY can perform a calibration step needed to > determine settings used by the other two PCIe PHYs. > > Calibration must be done with the combo PHY in PCIe mode, and to allow > this to occur independent of the eventual use for the PHY (PCIe or USB) > some PCIe-related properties must be supplied: clocks; resets; and a > syscon phandle. > > Signed-off-by: Alex Elder <elder@xxxxxxxxxxxx> > --- > .../bindings/phy/spacemit,k1-combo-phy.yaml | 110 ++++++++++++++++++ > 1 file changed, 110 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml > new file mode 100644 > index 0000000000000..ed78083a53231 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml > @@ -0,0 +1,110 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SpacemiT K1 PCIe/USB3 Combo PHY > + > +maintainers: > + - Alex Elder <elder@xxxxxxxxxxxx> > + > +description: You need a '>' or the paragraphs formatting will not be maintained (should we ever render docs from this). > + Of the three PHYs on the SpacemiT K1 SoC capable of being used for > + PCIe, one is a combo PHY that can also be configured for use by a > + USB 3 controller. Using PCIe or USB 3 is a board design decision. > + > + The combo PHY is also the only PCIe PHY that is able to determine > + PCIe calibration values to use, and this must be determined before > + the other two PCIe PHYs can be used. This calibration must be > + performed with the combo PHY in PCIe mode, and is this is done > + when the combo PHY is probed. > + > + During normal operation, the PCIe or USB port driver is responsible > + for ensuring all clocks needed by a PHY are enabled, and all resets > + affecting the PHY are deasserted. However, for the combo PHY to > + perform calibration independent of whether it's later used for > + PCIe or USB, all PCIe mode clocks and resets must be defined. > + > +properties: > + compatible: > + const: spacemit,k1-combo-phy > + > + reg: > + items: > + - description: PHY control registers > + > + clocks: > + items: > + - description: DWC PCIe Data Bus Interface (DBI) clock > + - description: DWC PCIe application AXI-bus Master interface clock > + - description: DWC PCIe application AXI-bus Slave interface clock. End with a period or don't. Just be consistent. You need DWC PCIe clocks for your PHY? A ref clock would make sense, but these? I've never seen a PHY with a AXI master interface. > + > + clock-names: > + items: > + - const: dbi > + - const: mstr > + - const: slv > + > + resets: > + items: > + - description: DWC PCIe Data Bus Interface (DBI) reset > + - description: DWC PCIe application AXI-bus Master interface reset > + - description: DWC PCIe application AXI-bus Slave interface reset. Same here (on both points). > + - description: Global reset; must be deasserted for PHY to function > + > + reset-names: > + items: > + - const: dbi > + - const: mstr > + - const: slv > + - const: global > + > + spacemit,syscon-pmu: > + description: > + PHandle that refers to the APMU system controller, whose > + regmap is used in setting the mode > + $ref: /schemas/types.yaml#/definitions/phandle > + > + "#phy-cells": > + const: 1 > + description: > + The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines > + whether the PHY operates in PCIe or USB3 mode. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - reset-names > + - spacemit,syscon-pmu > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/spacemit,k1-syscon.h> > + combo_phy: phy@c0b10000 { Drop unused labels. > + compatible = "spacemit,k1-combo-phy"; > + reg = <0xc0b10000 0x1000>; > + clocks = <&syscon_apmu CLK_PCIE0_DBI>, > + <&syscon_apmu CLK_PCIE0_MASTER>, > + <&syscon_apmu CLK_PCIE0_SLAVE>; > + clock-names = "dbi", > + "mstr", > + "slv"; > + resets = <&syscon_apmu RESET_PCIE0_DBI>, > + <&syscon_apmu RESET_PCIE0_MASTER>, > + <&syscon_apmu RESET_PCIE0_SLAVE>, > + <&syscon_apmu RESET_PCIE0_GLOBAL>; > + reset-names = "dbi", > + "mstr", > + "slv", > + "global"; > + spacemit,syscon-pmu = <&syscon_apmu>; > + #phy-cells = <1>; > + status = "disabled"; > + }; > -- > 2.48.1 >
