On Tue, Sep 02, 2025 at 04:12:21PM GMT, Rob Herring wrote: > On Mon, Sep 01, 2025 at 01:59:15PM +0800, Jacky Chou wrote: > > ASPEED AST2600 provides one PCIe RC for Gen2 and AST2700 provides three > > PCIe RC for two Gen4 and one Gen2. All of these RCs have just one root > > port to connect to PCIe device. And also have Mem, I/O access, legacy > > interrupt and MSI. > > > > Signed-off-by: Jacky Chou <jacky_chou@xxxxxxxxxxxxxx> > > --- > > .../bindings/pci/aspeed,ast2600-pcie.yaml | 179 ++++++++++++++++++ > > 1 file changed, 179 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml > > new file mode 100644 > > index 000000000000..fe75bf2961c8 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml > > @@ -0,0 +1,179 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: ASPEED PCIe Root Complex Controller > > + > > +maintainers: > > + - Jacky Chou <jacky_chou@xxxxxxxxxxxxxx> > > + > > +description: > > + The ASPEED PCIe Root Complex controller provides PCI Express Root Complex > > + functionality for ASPEED SoCs, such as the AST2600 and AST2700. > > + This controller enables connectivity to PCIe endpoint devices, supporting > > + memory and I/O windows, MSI and legacy interrupts, and integration with > > + the SoC's clock, reset, and pinctrl subsystems. > > + > > +properties: > > + compatible: > > + enum: > > + - aspeed,ast2600-pcie > > + - aspeed,ast2700-pcie > > + > > + reg: > > + maxItems: 1 > > + > > + ranges: > > + minItems: 2 > > + maxItems: 2 > > + > > + interrupts: > > + maxItems: 1 > > + description: IntX and MSI interrupt > > + > > + resets: > > + items: > > + - description: PCIe controller reset > > + > > + reset-names: > > + items: > > + - const: h2x > > + > > + msi-parent: true > > + > > + aspeed,ahbc: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to the ASPEED AHB Controller (AHBC) syscon node. > > + This reference is used by the PCIe controller to access > > + system-level configuration registers related to the AHB bus. > > + To enable AHB access for the PCIe controller. > > + > > + aspeed,pciecfg: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to the ASPEED PCIe configuration syscon node. > > + This reference allows the PCIe controller to access > > + SoC-specific PCIe configuration registers. There are the others > > + functions such PCIe RC and PCIe EP will use this common register > > + to configure the SoC interfaces. > > + So these config registers are part of the PCIe domain? Is so, accessing them as syscon is wrong. You should configure the registers directly from the RC and EP controller drivers. > > + interrupt-controller: > > + description: Interrupt controller node for handling legacy PCI interrupts. s/legacy PCI interrupts/INTx > > + type: object > > + properties: > > + '#address-cells': > > + const: 0 > > + '#interrupt-cells': > > + const: 1 > > + interrupt-controller: true > > + > > + required: > > + - '#address-cells' > > + - '#interrupt-cells' > > + - interrupt-controller > > + > > + additionalProperties: false > > + > > +allOf: > > + - $ref: /schemas/pci/pci-host-bridge.yaml# > > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: aspeed,ast2600-pcie > > + then: > > + required: > > + - aspeed,ahbc > > + else: > > + properties: > > + aspeed,ahbc: false > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: aspeed,ast2700-pcie > > + then: > > + required: > > + - aspeed,pciecfg > > + else: > > + properties: > > + aspeed,pciecfg: false > > + > > +required: > > + - reg > > + - interrupts > > + - bus-range > > + - ranges > > + - resets > > + - reset-names > > + - msi-parent > > + - msi-controller > > + - interrupt-map-mask > > + - interrupt-map > > + - interrupt-controller > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/ast2600-clock.h> > > + > > + apb { > > + #address-cells = <1>; > > + #size-cells = <1>; > > No need to show this node. > > > + > > + pcie0: pcie@1e770000 { > > + compatible = "aspeed,ast2600-pcie"; > > + device_type = "pci"; > > + reg = <0x1e770000 0x100>; > > + linux,pci-domain = <0>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; > > + bus-range = <0x80 0xff>; Why bus number starts from 128? > > + > > + ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 > > + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; > > + > > + status = "disabled"; > > Examples should be enabled. Drop. > > > + > > + resets = <&syscon ASPEED_RESET_H2X>; > > + reset-names = "h2x"; > > + > > + #interrupt-cells = <1>; > > + msi-parent = <&pcie0>; > > There shouldn't be any need to point to yourself. > > > + msi-controller; > > + > > + aspeed,ahbc = <&ahbc>; > > + > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie_intc0 0>, > > + <0 0 0 2 &pcie_intc0 1>, > > + <0 0 0 3 &pcie_intc0 2>, > > + <0 0 0 4 &pcie_intc0 3>; > > + pcie_intc0: interrupt-controller { > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + > > + pcie@8,0 { > > + reg = <0x804000 0 0 0 0>; Why the device number starts from 8? If there are platform specific reasons behind this numbering scheme, it should be mentioned in the description. - Mani -- மணிவண்ணன் சதாசிவம்
