Radxa E20C provides one of its GbE ports through RTL8111H connected to
SoC's PCIe controller. Let's enable the controller and the PHY used by
it to allow usage of the port.
Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
---
.../boot/dts/rockchip/rk3528-radxa-e20c.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
index 12eec2c1db22..e880c7a7e674 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
@@ -171,6 +171,10 @@ vdd_logic: regulator-vdd-logic {
};
};
+&combphy {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vdd_arm>;
};
@@ -229,6 +233,13 @@ rgmii_phy: ethernet-phy@1 {
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pciem1_pins>, <&pcie_reset_g>;
+ reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
&pinctrl {
ethernet {
gmac1_rstn_l: gmac1-rstn-l {
@@ -256,6 +267,12 @@ wan_led_g: wan-led-g {
};
};
+ pcie {
+ pcie_reset_g: pcie-reset-g {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.50.1
