Hi, > + reg = <0x1 0x40000000 0x0 0x400000>, > + <0x0 0xfe4f0000 0x0 0x10000>, > + <0x0 0xfc000000 0x0 0x100000>; Aligning the address for reg and ranges will look better: reg = <0x1 0x40000000 0x0 0x400000>, <0x0 0xfe4f0000 0x0 0x010000>, <0x0 0xfc000000 0x0 0x100000>; BTW do we possibly need this? https://github.com/rockchip-linux/kernel/commit/e9397245c4b1bd62ef929d221e20225d58467dc7 > + clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, > + <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>, > + <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE_PHY>; <&cru PCLK_PCIE_PHY> has already been defined in the combphy node, is it repeated here? Thanks, Chukun
