On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote: > Each PCIe controller on sa8775p includes 'link_down'reset on hardware, > document it. Please describe what this reset does here as I asked you to earlier. > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> > --- > .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml > index 4b91b5608013..510c9e1c28e1 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml > @@ -66,11 +66,14 @@ properties: > - const: global > > resets: > - maxItems: 1 > + items: > + - description: PCIe controller reset > + - description: PCIe link down reset > > reset-names: > items: > - - const: pci > + - const: pci # PCIe core reset > + - const: link_down # PCIe link down reset I think you can drop the comments since you already describe the resets above. Johan
