Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
document it.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx>
---
.../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index 4b91b5608013..510c9e1c28e1 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -66,11 +66,14 @@ properties:
- const: global
resets:
- maxItems: 1
+ items:
+ - description: PCIe controller reset
+ - description: PCIe link down reset
reset-names:
items:
- - const: pci
+ - const: pci # PCIe core reset
+ - const: link_down # PCIe link down reset
required:
- interconnects
@@ -166,8 +169,10 @@ examples:
power-domains = <&gcc PCIE_0_GDSC>;
- resets = <&gcc GCC_PCIE_0_BCR>;
- reset-names = "pci";
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
--
2.34.1
