On Fri, 2025-06-13 at 11:30 +0800, Jacky Chou wrote: > The PCIe RC PERST uses SSPRST# as PERST# and enable this pin > to output. > > Signed-off-by: Jacky Chou <jacky_chou@xxxxxxxxxxxxxx> > --- > drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > index 5a7cd0a88687..c751703acdb9 100644 > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > @@ -17,6 +17,7 @@ > #include "../pinctrl-utils.h" > #include "pinctrl-aspeed.h" > > +#define SCU040 0x040 /* Reset Control Set 1 */ > #define SCU400 0x400 /* Multi-function Pin Control #1 */ > #define SCU404 0x404 /* Multi-function Pin Control #2 */ > #define SCU40C 0x40C /* Multi-function Pin Control #3 */ > @@ -52,7 +53,7 @@ > #define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */ > #define SCUC20 0xC20 /* PCIE configuration Setting Control */ > > -#define ASPEED_G6_NR_PINS 256 > +#define ASPEED_G6_NR_PINS 258 > > #define M24 0 > SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); > @@ -1636,6 +1637,12 @@ FUNC_DECL_1(USB11BHID, USBB); > FUNC_DECL_1(USB2BD, USBB); > FUNC_DECL_1(USB2BH, USBB); > > +#define D7 257 > +SIG_EXPR_LIST_DECL_SESG(D7, RCRST, PCIERC1, SIG_DESC_SET(SCU040, 19), The documentation for SCU040[19] says it will assert the reset. I expect that's not what's desired. > + SIG_DESC_SET(SCU500, 24)); SCU500[24] seems okay. > +PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, RCRST)); > +FUNC_GROUP_DECL(PCIERC1, D7); It only makes sense to describe pins with multiple functions. The other function this pin has is the reset line for the secondary service processor. Can we describe that too? Andrew
