On 6/11/25 19:51, Niklas Cassel wrote: > As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds > greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link > training completes before sending a Configuration Request. > > Add this delay in dw_pcie_wait_for_link(), after the link is reported as > up. The delay will only be performed in the success case where the link > came up. > > DWC glue drivers that have a link up IRQ (drivers that set > use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they > perform this delay in their threaded link up IRQ handler. > > Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx> Reviewed-by: Damien Le Moal <dlemoal@xxxxxxxxxx> -- Damien Le Moal Western Digital Research
