On 6/11/25 19:51, Niklas Cassel wrote:
> Commit 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect Link
> Up") changed so that we no longer call dw_pcie_wait_for_link(), and instead
> enumerate the bus directly after receiving the Link Up IRQ.
>
> This means that there is no longer any delay between link up and the bus
> getting enumerated.
>
> As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
> training completes before sending a Configuration Request.
>
> Add this delay in the threaded link up IRQ handler in order to satisfy
> the requirements of the PCIe spec.
>
> Fixes: 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect Link Up")
> Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c789e3f85655..0a627f3b5e2c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1565,6 +1565,13 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
>
> if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
> dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
Same comment here as for the dw-rockchip. Sleep before printing the message ?
> + /*
> + * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports
> + * Link speeds greater than 5.0 GT/s, software must wait a
> + * minimum of 100 ms after Link training completes before
> + * sending a Configuration Request.
> + */
> + msleep(PCIE_T_RRS_READY_MS);
> /* Rescan the bus to enumerate endpoint devices */
> pci_lock_rescan_remove();
> pci_rescan_bus(pp->bridge->bus);
Either way,
Reviewed-by: Damien Le Moal <dlemoal@xxxxxxxxxx>
--
Damien Le Moal
Western Digital Research
