On Tue, Jun 10, 2025 at 03:07:44PM -0500, Bjorn Helgaas wrote: > On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote: > This stuff: > > #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) > #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) > #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) > #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) > #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0) > > *Looks* like it might be duplicates of: > > #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ > #define PCI_EXP_DEVCTL 0x08 /* Device Control */ > #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */ Hi again Bjorn, Your message reminded me of something that may be important. During my debugging I had the mild impression L0s capability is not being cleared from Link Capabilities Register in the presence of "aspm-no-l0s" DT property. I can't confirm it right now but I might revisit this later on. From what I've seen it can only be cleared from inside the port init in pcie-rockchip.c and does nothing in present form. Not a clear, confirmable report but something to watch out for... Regards, Geraldo Nascimento
