On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote: > Link Control and Status Register 2 is not present in current > pcie-rockchip.h definitions. Add it in preparation for > setting it before Gen2 retraining. > > Signed-off-by: Geraldo Nascimento <geraldogabriel@xxxxxxxxx> > --- > drivers/pci/controller/pcie-rockchip.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 14954f43e5e9..7a84899d3812 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -166,6 +166,9 @@ > #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) > #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) > #define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) > +#define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0) > +#define PCIE_RC_CONFIG_LCS_2_TLS_25 BIT(0) > +#define PCIE_RC_CONFIG_LCS_2_TLS_50 BIT(1) This stuff: #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0) *Looks* like it might be duplicates of: #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ #define PCI_EXP_DEVCTL 0x08 /* Device Control */ #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */ #define PCI_EXP_LNKCTL 0x10 /* Link Control */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */ where the PCIe Capability is at (PCIE_RC_CONFIG_BASE + 0xc0). If so, can you please rework these to use the existing PCI_EXP_* definitions, including the fields inside? > #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) > #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) > #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) > -- > 2.49.0 >
