On Wed, Apr 16, 2025 at 04:13:11PM +0800, Richard Zhu wrote:
> ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through Beacon
> or PERST# De-assertion
>
> When the auxiliary power is not available, the controller cannot exit from
> L23 Ready with beacon or PERST# de-assertion when main power is not
> removed.
>
> Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
>
> The workaround is irrespective of Vaux presence in remote partner.
> In the other words, this workaround should work whatever the remote
> partner has the Vaux or not.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
- Mani
> Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 7c60b712480a..016b86add959 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -48,6 +48,8 @@
> #define IMX95_PCIE_SS_RW_REG_0 0xf0
> #define IMX95_PCIE_REF_CLKEN BIT(23)
> #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
> +#define IMX95_PCIE_SS_RW_REG_1 0xf4
> +#define IMX95_PCIE_SYS_AUX_PWR_DET BIT(31)
>
> #define IMX95_PE0_GEN_CTRL_1 0x1050
> #define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0)
> @@ -227,6 +229,19 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
>
> static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> + /*
> + * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> + * Through Beacon or PERST# De-assertion
> + *
> + * When the auxiliary power is not available, the controller
> + * cannot exit from L23 Ready with beacon or PERST# de-assertion
> + * when main power is not removed.
> + *
> + * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
> + */
> + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> + IMX95_PCIE_SYS_AUX_PWR_DET);
> +
> regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
> IMX95_PCIE_PHY_CR_PARA_SEL,
> --
> 2.37.1
>
--
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