On Mon, Apr 14, 2025 at 11:09:13AM +0530, Krishna Chaitanya Chundru wrote:
> Move phy, perst, to root port from the controller node.
>
> Rename perst-gpios to reset-gpios to align with the expected naming
> convention of pci-bus-common.yaml.
Note that the cover letter doesn't land in the git history. Anybody
browsing file history would have hard time understanding the reason for
the change.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 5 ++++-
> arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++-
> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++-
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++----
I can only hope that after the series is landed, there will be a
followup from you, convering all other platforms.
> 4 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 7a36c90ad4ec8b52f30b22b1621404857d6ef336..3dd58986ad5da0f898537a51715bb5d0fecbe100 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -709,8 +709,11 @@ &mdss_edp_phy {
> status = "okay";
> };
>
> +&pcie1_port0 {
> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +};
> +
> &pcie1 {
> - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
>
> pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> index 2ba4ea60cb14736c9cfbf9f4a9048f20a4c921f2..ff11d85d015bdab6a90bd8a0eb9113a339866953 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> @@ -472,10 +472,13 @@ &pcie1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;
>
> - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> vddpe-3v3-supply = <&pp3300_ssd>;
> };
>
> +&pcie1_port0 {
> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +};
> +
> &pm8350c_pwm {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 7370aa0dbf0e3f9e7a3e38c3f00686e1d3dcbc9f..3209bb15dfec36299cabae07d34f3dc82db6de77 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -414,9 +414,12 @@ &lpass_va_macro {
> vdd-micb-supply = <&vreg_bob>;
> };
>
> +&pcie1_port0 {
> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +};
> +
> &pcie1 {
> status = "okay";
> - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
>
> vddpe-3v3-supply = <&nvme_3v3_regulator>;
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 0f2caf36910b65c398c9e03800a8ce0a8a1f8fc7..376fabf3b4eac34d75bb79ef902c9d83490c45f7 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2271,9 +2271,6 @@ pcie1: pcie@1c08000 {
>
> power-domains = <&gcc GCC_PCIE_1_GDSC>;
>
> - phys = <&pcie1_phy>;
> - phy-names = "pciephy";
> -
> pinctrl-names = "default";
> pinctrl-0 = <&pcie1_clkreq_n>;
>
> @@ -2284,7 +2281,7 @@ pcie1: pcie@1c08000 {
>
> status = "disabled";
>
> - pcie@0 {
> + pcie1_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> @@ -2292,6 +2289,7 @@ pcie@0 {
> #address-cells = <3>;
> #size-cells = <2>;
> ranges;
> + phys = <&pcie1_phy>;
> };
> };
>
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
