On Sat, Aug 30, 2025 at 3:45 AM Marcelo Schmitt
<marcelo.schmitt@xxxxxxxxxx> wrote:
>
> Set AD4030 series device to do two data bit transitions per clock cycle per
> active lane when specified by firmware. The dual data rate (DDR) feature is
> available only for host clock mode and echo clock mode.
...
> struct ad4030_state {
> enum ad4030_out_mode mode;
> enum ad4030_lane_mode lane_mode;
> enum ad4030_clock_mode clock_mode;
> + bool ddr;
I believe you run `pahole` each time you modify the data type like this.
> /* offload sampling spi message */
> struct spi_transfer offload_xfer;
> struct spi_message offload_msg;
...
> else
> offload_bpw = data_width / (1 << st->lane_mode);
With the previous comment WRT right shift...
> + if (st->ddr)
> + offload_bpw /= 2;
...this also can use right shift, but I understand that 2 is more
explicit to show the point of DDR (as "double").
...
> + /* DDR is only valid for echo clock and host clock modes */
> + if (ret == AD4030_ECHO_CLOCK_MODE || ret == AD4030_CLOCK_HOST_MODE) {
> + st->ddr = device_property_read_bool(dev, "adi,dual-data-rate");
> + reg_modes |= FIELD_PREP(AD4030_REG_MODES_MASK_DDR_MODE, st->ddr);
FIELD_MODIFY()?
> + }
--
With Best Regards,
Andy Shevchenko
