Re: [PATCH 3/5] arm64: dts: qcom: lemans-evk: Extend peripheral and subsystem support

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On 8/27/2025 7:05 AM, Dmitry Baryshkov wrote:
On Tue, Aug 26, 2025 at 11:51:02PM +0530, Wasim Nazir wrote:
Enhance the Qualcomm Lemans EVK board file to support essential
peripherals and improve overall hardware capabilities, as
outlined below:
   - Enable GPI (Generic Peripheral Interface) DMA-0/1/2 and QUPv3-0/2
     controllers to facilitate DMA and peripheral communication.
   - Add support for PCIe-0/1, including required regulators and PHYs,
     to enable high-speed external device connectivity.
   - Integrate the TCA9534 I/O expander via I2C to provide 8 additional
     GPIO lines for extended I/O functionality.
   - Enable the USB0 controller in device mode to support USB peripheral
     operations.
   - Activate remoteproc subsystems for supported DSPs such as Audio DSP,
     Compute DSP-0/1 and Generic DSP-0/1, along with their corresponding
     firmware.
   - Configure nvmem-layout on the I2C EEPROM to store data for Ethernet
     and other consumers.
   - Enable the QCA8081 2.5G Ethernet PHY on port-0 and expose the
     Ethernet MAC address via nvmem for network configuration.
     It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY.
   - Add support for the Iris video decoder, including the required
     firmware, to enable video decoding capabilities.
   - Enable SD-card slot on SDHC.

Co-developed-by: Viken Dadhaniya <viken.dadhaniya@xxxxxxxxxxxxxxxx>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@xxxxxxxxxxxxxxxx>
Co-developed-by: Sushrut Shree Trivedi <quic_sushruts@xxxxxxxxxxx>
Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@xxxxxxxxxxx>
Co-developed-by: Nirmesh Kumar Singh <quic_nkumarsi@xxxxxxxxxxx>
Signed-off-by: Nirmesh Kumar Singh <quic_nkumarsi@xxxxxxxxxxx>
Co-developed-by: Krishna Kurapati <krishna.kurapati@xxxxxxxxxxxxxxxx>
Signed-off-by: Krishna Kurapati <krishna.kurapati@xxxxxxxxxxxxxxxx>
Co-developed-by: Mohd Ayaan Anwar <quic_mohdayaa@xxxxxxxxxxx>
Signed-off-by: Mohd Ayaan Anwar <quic_mohdayaa@xxxxxxxxxxx>
Co-developed-by: Dikshita Agarwal <quic_dikshita@xxxxxxxxxxx>
Signed-off-by: Dikshita Agarwal <quic_dikshita@xxxxxxxxxxx>
Co-developed-by: Monish Chunara <quic_mchunara@xxxxxxxxxxx>
Signed-off-by: Monish Chunara <quic_mchunara@xxxxxxxxxxx>
Co-developed-by: Vishal Kumar Pal <quic_vispal@xxxxxxxxxxx>
Signed-off-by: Vishal Kumar Pal <quic_vispal@xxxxxxxxxxx>
Signed-off-by: Wasim Nazir <wasim.nazir@xxxxxxxxxxxxxxxx>
---
  arch/arm64/boot/dts/qcom/lemans-evk.dts | 387 ++++++++++++++++++++++++++++++++
  1 file changed, 387 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index 9e415012140b..642b66c4ad1e 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -16,7 +16,10 @@ / {
  	compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";
aliases {
+		ethernet0 = &ethernet0;
+		mmc1 = &sdhc;
  		serial0 = &uart10;
+		serial1 = &uart17;
  	};
chosen {
@@ -46,6 +49,30 @@ edp1_connector_in: endpoint {
  			};
  		};
  	};
+
+	vmmc_sdc: regulator-vmmc-sdc {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc_sdc";
Non-switchable, always enabled?

+
+		regulator-min-microvolt = <2950000>;
+		regulator-max-microvolt = <2950000>;
+	};
+
+	vreg_sdc: regulator-vreg-sdc {
+		compatible = "regulator-gpio";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <2950000>;
+		regulator-name = "vreg_sdc";
+		regulator-type = "voltage";
This one also can not be disabled?

+
+		startup-delay-us = <100>;
+
+		gpios = <&expander1 7 GPIO_ACTIVE_HIGH>;
+
+		states = <1800000 0x1
+			  2950000 0x0>;
+	};
  };
&apps_rsc {
@@ -277,6 +304,161 @@ vreg_l8e: ldo8 {
  	};
  };
+&ethernet0 {
+	phy-handle = <&hsgmii_phy0>;
+	phy-mode = "2500base-x";
+
+	pinctrl-0 = <&ethernet0_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,ps-speed = <1000>;
+
+	nvmem-cells = <&mac_addr0>;
+	nvmem-cell-names = "mac-address";
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hsgmii_phy0: ethernet-phy@1c {
+			compatible = "ethernet-phy-id004d.d101";
+			reg = <0x1c>;
+			reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&gpi_dma0 {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpi_dma2 {
+	status = "okay";
+};
+
+&i2c18 {
+	status = "okay";
+
+	expander0: pca953x@38 {
+		compatible = "ti,tca9538";
+		#gpio-cells = <2>;
+		gpio-controller;
+		reg = <0x38>;
+	};
+
+	expander1: pca953x@39 {
+		compatible = "ti,tca9538";
+		#gpio-cells = <2>;
+		gpio-controller;
+		reg = <0x39>;
+	};
+
+	expander2: pca953x@3a {
+		compatible = "ti,tca9538";
+		#gpio-cells = <2>;
+		gpio-controller;
+		reg = <0x3a>;
+	};
+
+	expander3: pca953x@3b {
+		compatible = "ti,tca9538";
+		#gpio-cells = <2>;
+		gpio-controller;
+		reg = <0x3b>;
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+		pagesize = <64>;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mac_addr0: mac-addr@0 {
+				reg = <0x0 0x6>;
+			};
+		};
+	};
+};
+
+&iris {
+	firmware-name = "qcom/vpu/vpu30_p4_s6.mbn";
Should it be just _s6.mbn or _s6_16mb.mbn?

+
+	status = "okay";
+};
+
  &mdss0 {
  	status = "okay";
  };
@@ -323,14 +505,196 @@ &mdss0_dp1_phy {
  	status = "okay";
  };
+&pcie0 {
+	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
I think Mani has been asking lately to define these GPIOs inside the
port rather than in the host controller.

+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_default_state>;
+
+	status = "okay";
+};
+
[...]

@@ -356,6 +720,29 @@ &ufs_mem_phy {
  	status = "okay";
  };
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_dwc3 {
+	dr_mode = "peripheral";
Is it actually peripheral-only?

Hi Dmitry,

HW supports OTG mode also, but for enabling OTG we need below mentioned
driver changes in dwc3-qcom.c :

a) dwc3 core callback registration by dwc3 glue driver; this change is under
    review in upstream.
b) vbus supply enablement for host mode; this change is yet to be submitted
    to upstream.

Post the above mentioned driver changes, we are planning to enable OTG on
usb0.

- Sushrut

+};
+




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