On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote:
> From: Monish Chunara <quic_mchunara@xxxxxxxxxxx>
>
> Introduce the SDHC v5 controller node for the Lemans platform.
> This controller supports either eMMC or SD-card, but only one
> can be active at a time. SD-card is the preferred configuration
> on Lemans targets, so describe this controller.
>
> Define the SDC interface pins including clk, cmd, and data lines
> to enable proper communication with the SDHC controller.
>
> Signed-off-by: Monish Chunara <quic_mchunara@xxxxxxxxxxx>
> Co-developed-by: Wasim Nazir <wasim.nazir@xxxxxxxxxxxxxxxx>
> Signed-off-by: Wasim Nazir <wasim.nazir@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 99a566b42ef2..a5a3cdba47f3 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint {
> };
> };
>
> + sdhc: mmc@87c4000 {
> + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x087c4000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>;
> + clock-names = "iface", "core";
> +
> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> +
> + iommus = <&apps_smmu 0x0 0x0>;
> + dma-coherent;
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> +
> + no-sdio;
> + no-mmc;
> + bus-width = <4>;
This is the board configuration, it should be defined in the EVK DTS.
> + qcom,dll-config = <0x0007642c>;
> + qcom,ddr-config = <0x80040868>;
> +
> + status = "disabled";
> + };
> +
> usb_0_hsphy: phy@88e4000 {
> compatible = "qcom,sa8775p-usb-hs-phy",
> "qcom,usb-snps-hs-5nm-phy";
> @@ -5643,6 +5673,46 @@ qup_uart21_rx: qup-uart21-rx-pins {
> function = "qup3_se0";
> };
> };
> +
> + sdc_default: sdc-default-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> + };
> +
> + sdc_sleep: sdc-sleep-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + drive-strength = <2>;
> + bias-bus-hold;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + drive-strength = <2>;
> + bias-bus-hold;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + drive-strength = <2>;
> + bias-bus-hold;
> + };
> + };
> };
>
> sram: sram@146d8000 {
>
> --
> 2.51.0
>
--
With best wishes
Dmitry
