In preparation of adding iris (video acceleration) for Qualcomm X1E80100, enable support for the video clock controller and additional needed reset controls. Since iris in X1E is largely identical to SM8550, reuse the existing videocc-sm8550 driver with slightly adjusted PLL frequencies and adapt the reset definitions from the SM8550 GCC driver. Signed-off-by: Stephan Gerhold <stephan.gerhold@xxxxxxxxxx> --- Changes in v2: - Fix commit message of PATCH 5/6 (reset definitions are just copied as-is from gcc-sm8550 actually) (Konrad) - PATCH 6/6: Use GCC_VIDEO_AHB for videocc instead of GCC_QMIP_VIDEO_VCODEC_AHB_CLK (Konrad) - Link to v1: https://lore.kernel.org/r/20250701-x1e-videocc-v1-0-785d393be502@xxxxxxxxxx --- Stephan Gerhold (6): dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets clk: qcom: gcc-x1e80100: Add missing video resets arm64: dts: qcom: x1e80100: Add videocc .../bindings/clock/qcom,sm8450-videocc.yaml | 1 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 15 +++++++++++ drivers/clk/qcom/Kconfig | 3 +-- drivers/clk/qcom/gcc-x1e80100.c | 2 ++ drivers/clk/qcom/videocc-sm8550.c | 29 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,x1e80100-gcc.h | 2 ++ 6 files changed, 50 insertions(+), 2 deletions(-) --- base-commit: 0672fe83ed07387afb88653ab3b5dae4c84cf3ce change-id: 20250701-x1e-videocc-10f1f2257463 Best regards, -- Stephan Gerhold <stephan.gerhold@xxxxxxxxxx>
