On 2025/3/29 2:22, Catalin Marinas wrote:
> On Thu, Mar 20, 2025 at 05:41:14PM +0000, Jonathan Cameron wrote:
>> +struct system_cache_flush_method {
>> + int (*invalidate_memregion)(int res_desc,
>> + phys_addr_t start, size_t len);
>> +};
> [...]
>> +int cpu_cache_invalidate_memregion(int res_desc, phys_addr_t start, size_t len)
>> +{
>> + guard(spinlock_irqsave)(&scfm_lock);
>> + if (!scfm_data)
>> + return -EOPNOTSUPP;
>> +
>> + return scfm_data->invalidate_memregion(res_desc, start, len);
>> +}
>
> WBINVD on x86 deals with the CPU caches as well. Even the API naming in
> Linux implies CPU caches. IIUC, devices registering to the above on Arm
> SoCs can only deal with system caches. Is it sufficient?
>
The device driver who register this method should handle this. If the
hardware support maintaining the coherency among the system, for example
on system cache invalidation the hardware is also able to invalidate the
involved cachelines on all the subordinate caches (L1/L2/etc, by back
invalidate snoop or other ways), then software don't need to invalidate
the non-system cache explicitly. Otherwise the driver need to explicitly
invalidate the non-system cache explicitly in their
scfm_data::invalidate_memregion() method. Here in the generally code we
simply don't know the capability of the hardware.
Thanks.
