On 8/19/2025 8:02 PM, Borislav Petkov wrote:
On Tue, Aug 19, 2025 at 09:45:02AM +0530, Upadhyay, Neeraj wrote:Maybe change it to below? /* * Valid APIC_IRR/SAVIC_ALLOWED_IRR registers are at 16 bytes strides * from their respective base offset. */ if (WARN_ONCE(!(IS_ALIGNED(reg - APIC_IRR, 16) || IS_ALIGNED(reg - SAVIC_ALLOWED_IRR, 16)), "Misaligned APIC_IRR/ALLOWED_IRR APIC register read offset 0x%x", reg))Let's beef that up some more with a crystal-clear explanation what is going on here so that readers don't have to stop and stare for 5 mins before they grok what this is doing: /* * Valid APIC_IRR/SAVIC_ALLOWED_IRR registers are at 16 bytes strides from * their respective base offset. APIC_IRRs are in the range * * (0x200, 0x210, ..., 0x270) * * while the SAVIC_ALLOWED_IRR range starts 4 bytes later, in the rangea * * (0x204, 0x214, ..., 0x274). * * Filter out everything else. */ if (WARN_ONCE(!(IS_ALIGNED(reg, 16) || IS_ALIGNED(reg - 4, 16)), "Misaligned APIC_IRR/ALLOWED_IRR APIC register read offset 0x%x", reg));
Ok, looks good. Thanks! - Neeraj
