On 8/20/2025 3:23 AM, Borislav Petkov wrote:
On Mon, Aug 11, 2025 at 03:14:30PM +0530, Neeraj Upadhyay wrote:
Initialize the APIC ID in the Secure AVIC APIC backing page with
the APIC_ID msr value read from Hypervisor. CPU topology evaluation
later during boot would catch and report any duplicate APIC ID for
two CPUs.
Reviewed-by: Tianyu Lan <tiala@xxxxxxxxxxxxx>
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@xxxxxxx>
---
Changes since v8:
- Added Tianyu's Reviewed-by.
- Code cleanup.
arch/x86/kernel/apic/x2apic_savic.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index 86a522685230..55edc6c30ba4 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -141,6 +141,12 @@ static void savic_setup(void)
enum es_result res;
unsigned long gpa;
+ /*
+ * Before Secure AVIC is enabled, APIC msr reads are intercepted.
s/msr/MSR/g
Please check your whole text for such acronyms.
Ok, will fix this in all patches.
- Neeraj
