On 8/27/2025 3:23 PM, Huang, Kai wrote: > On Tue, 2025-08-26 at 20:28 +0530, Nikunj A. Dadhania wrote: >> >> On 8/26/2025 3:36 PM, Huang, Kai wrote: >>> On Mon, 2025-08-25 at 15:20 +0000, Nikunj A Dadhania wrote: >>> >>> Looking at the code change, IIUC the PML code that is moved to x86 common >>> assumes AMD's PML also follows VMX's behaviour: >>> >>> 1) The PML buffer is a 4K page; >>> 2) The hardware records the dirty GPA in backwards to the PML buffer >>> >>> Could we point this out in the changelog? >> >> Ack, will add in the next revision > > Thanks. Maybe one more to point out: > > 3) AMD PML also clears bit 11:0 when recording the GPA. Sure.
